Hackaday

Accurate Digital Clock Keeps Ticking With FPGA

Even the most punctual among us are content to synchronize their clocks to external time sources like navigation satellite constellations, network time servers, frequency-controlled AC mains, or ...
EDN

Mixed-signal FPGA integrates soft ARM7 IP core

New IP Core and Enhanced Design Infrastructure Enable Rapid and Easy Deployment of ARM7-Based, Mixed-Signal Systems Mountain View, Calif.—Underscoring its efforts to simplify the design of embedded ...
Electronic Design

Timing Decisions 102: Optimize Your Clock Tree

The importance of timing requirements and jitter budgets for FPGAs, ASICs, and SoCs. How to utilize the information portrayed in a clock tree to choose the most well-suited clock generator for your ...
EDN

Mixed-signal FPGA from Actel unlocks new design possibilities

Actel Corporation has announced the immediate availability of the Actel Fusion Programmable System Chip (PSC), the world's first mixed-signal FPGA family. By integrating mixed-signal analog, Flash ...
Semiconductor Engineering

The Design Challenges Of Clock Integrity And Clock Jitter

Signal integrity is one of the many challenges faced by chip designers. Deep submicron technologies are unfriendly hosts for the nice, clean signals desired. The culprits that compromise signal ...