Semiconductor Engineering

Foundation IP For 7nm FinFETs: Design And Implementation

Learn about the challenges of IP design and implementation for 7nm FinFETs. Along with the performance and area benefits that the node brings, designers must understand the significant technical ...
Nasdaq

TSMC Certifies Synopsys' Digital and Custom Design Platforms on TSMC 5nm FinFET Process Technology

IC Compiler II and Design Compiler Graphical provide a complete digital implementation flow delivering optimized power, performance, area, and full via pillar support StarRC, PrimeTime, NanoTime, and ...
Nasdaq

Keysight, Synopsys, and Ansys Accelerate RFIC Semiconductor Design with New Reference Flow for TSMC's Most Advanced 4nm RF FinFET Process

New reference flow offers open, efficient radio frequency design solution that supports streamlined migration from previous process nodes Industry-leading electromagnetic simulation tools boost 5G/6G ...
Semiconductor Engineering

ESD Signoff No Longer A “Nice to Have” In FinFET Design Era

As the semiconductor industry transitions to finFETs, reliability challenges are increasing. ESD designers are challenged with new issues that would require significant rethinking and redesign of ...
Business Wire

Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process ...
NextBigFuture

finFETs Could be Smaller and at least Five Times Faster than silicon Transistors

Researchers are making progress in developing new types of transistors, called finFETs, which use a finlike structure instead of the conventional flat design, possibly enabling engineers to create ...
Electronic Design

Identifying transistor-level yield limiters in the FinFET era

As the digital semiconductor manufacturing process moves into the FinFET era, more and more front-end-of-line (FEOL) defects are observed due to extremely small feature size and complex manufacturing ...
EDN

FinFETs drive smarter choices for physical IP

The semiconductor industry faces a major change in the way that ICs are made in order to keep improving performance and density, a change that has potential ramifications for design methodologies.
Business Wire

Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...
Design-Reuse

UMC Announces Release of 14nm eHV FinFET Platform, Advancing Innovation in Next-Generation Smartphone Displays

HSINCHU, Taiwan — United Microelectronics Corporation (NYSE: UMC; TWSE: 2303) (“UMC”), a leading global semiconductor foundry, today announced the release of its 14nm embedded high-voltage (eHV) ...
EDN

Synopsys Implementation Solution Included in TSMC 16-nm Reference Flow for FinFET Design

Synopsys, Inc. (Nasdaq: SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced delivery of a comprehensive design ...
Purdue University

New 'finFET' promising for smaller transistors, more powerful chips

Purdue University researchers are making progress in developing a new type of transistor that uses a finlike structure instead of the conventional flat design, possibly enabling engineers to create ...