Learn how using formal verification can take you beyond the limitations of directed-random simulation when debugging silicon. A series of case studies provide real-world usage examples of Jasper ...

Using the right methodology for applying and using products within a design project is critical to getting a high return on investment (ROI). This is especially true in emerging areas such as formal ...

This article is about our experience in applying formal verification techniques to an ASIC design in a large communication system. When we, in the Alcatel-Lucent IC design group in Nürnberg, Germany, ...

The automotive functional safety standard, ISO 26262, defines two verification requirements for integrated circuits used in automotive applications—systematic failure verification and random hardware ...

The most effective functional verification environments employ multiple analysis technologies, where the strengths of each are combined to reinforce each other to help ensure that the device under ...

Formal verification is poised to take on an increasingly significant role in automotive security, building upon its already widespread use in safety-critical applications. Formal has been essential ...

Formal technology is playing an increasing role in the debug process, and some fundamental new directions are being explored to make debug more automated. While much of the design and verification ...

Formal verification, which uses mathematical analysis rather than simulation tests, has been available in commercial EDA tools for more than 20 years and in academia much longer. As with many new ...