IEEE

A 0.53-pJ/bit 5 × 10 Gb/s/pin Single-Ended Transceiver With Reconfigurable 4-Aggressor Crosstalk Cancellation for HBM Interfaces

Abstract: This paper presents a high-bandwidth memory (HBM) PHY interface employing a reconfigurable differentiator-based crosstalk cancellation (XTC) scheme to mitigate coupling noise arising in high ...
IEEE

37.2 A 47.0Tb/s/mm 112Gb/s/pin PAM4 Single-Ended Transceiver Featuring 4-Aggressor Crosstalk Cancellation and Supply-Noise Tolerance for Short-Reach Memory Interfaces

Abstract: This paper presents a five-lane 112Gb/s/pin PAM4 single-ended transceiver in 28nm CMOS for high-density short-reach memory interfaces. Low-power triple-equalization, 4-aggressor ...